The present invention relates to a system and method for aligning two or more clock domains. More particularly, the present invention relates to a system and method for aligning transmit and receive clocks in a bus system.
FIG. 1A conceptually illustrates a bus system. The bus system generally comprises a master 3 and one or more slave devices (2a . . . 2n) connected via a channel comprising a number of signal lines or buses. Typically, a bi-directional bus communicates data between master 3 and slave devices (2a . . . 2n). Control information is communicated via the same or via a separate bus (not shown). Data and/or control information are communicated in relation to one or more clock signals. Master 3 is associated with an application 1. Application 1 may take many forms including a microprocessor, a memory controller, a graphics controller, etc. Application 1 may incorporate master 3 or be separately implemented.
In the example, shown in FIG. 1A, an externally generated Clock-To-Master (CTM), or first system clock signal, travels through the slave devices towards the master. At the master, CTM is turned around to form a Clock-From-Master (CFM), or a second system clock signal, which travel backs through the slave devices in a direction away from the master. In contemporary bus systems, the master and/or the slave devices typically includes an interface circuit (not shown) which controls the data and control information signals communicated between the master and the slave devices.
The relationship between application 1 and master 3 is further illustrated in FIG. 1B. Master 3 typically includes one or more delay locked loop (DLL) circuit(s), or similar circuit(s), which generates a receive clock (rclk) and a transmit clock (tclk). Generally speaking, the receive clock (rclk) controls the receiver functions in master 3 and the transmit clock (tclk) controls the transmit or data output functions in master 3. Thus, rclk and tclk define separate clock domains. This concept is illustrated by the relationships between receiver 3a, output driver 3b, and DLL 4 of FIG. 1B.
The receive clock (rclk) in the master is normally aligned with the knowledge that data being sent from the slave devices is communicated in a known relationship to CTM, and that this relationship is maintained as both the data signals and CTM traverse the channel towards the master. In other words, the receive clock (rclk) is normally phase aligned in a known relationship to CTM. This relationship is designed to maximize the timing margin for sampling the data at master 3. In many contemporary bus systems, data is transmitted 90° ahead of its corresponding CTM edge. As illustrated in FIG. 2, this relationship requires that the receive clock (rclk) lag CTM by a period of time equal to the nominal setup time for the receiver (TSETUP—IR).
To achieve the foregoing, DLL 4 may be used. FIG. 3 illustrates an exemplary clock recovery circuit yielding the desired relationship comprising DLL 4 and flip-flop circuits (5a . . . 5e). Use of the receiver in the master as a phase detector for the DLL circuit assures that rclk properly lags CTM by the period TSETUP—IR.
Referring to again to FIG. 1B, the transmit clock (tclk) is aligned with the knowledge that data being sent from the master to the slave devices is communicated with a known relationship to CFM, and that this relationship is maintained as both the data and CFM traverse the channel away from the master. This relationship is designed to maximize the timing margin for sampling the data at the slave devices.
In contemporary bus systems, it is common for data to be communicated 90° ahead of the corresponding CFM edge. Since there is a known, finite delay for the data traversing the output drivers in the master (output driver delay, TOD), achieving the desired data to tclk timing relationship requires that the transmit clock (tclk) be (90°+TOD) ahead of the corresponding CFM edge. This relationship is illustrated in FIG. 4.
A clock recovery circuit yielding the desired tclk relationships is shown in FIG. 5. Within this exemplary circuit, DLL 6 is used to align the transmit clock (tclk) which is applied to output drivers 10a, 10b . . . 10n. The feedback path uses a 90° block 9 and a dummy output driver circuit 8 to achieve the desired phase relationship. A Zero degree Phase Detector (ZPD) is used to compare the feedback signal to CFM and drive DLL 6.
In addition to rclk and tclk, master 3 typically generates a third reference signal, Synclk. Synclk is used to control data exchanges between application 1 and master 3. That is, Synclk provides a reference for data signals received from the application by the master and for data signal sent from the master to the application. As illustrated in FIG. 1B, some contemporary bus systems formed Synclk by a dividing down the receiver clock (rclk).in divider circuit 3c. Thus, the timing relationships for signals being communicated between the master and the application are ultimately referenced to Synclk which in turn is a product of rclk.
Unfortunately, as suggested above, a great number of control and data signals in the master must necessarily be referenced to tclk instead of Synclk/rclk. The existence of separate tclk and rclk domains within a bus system creates a number of synchronization concerns. For example, data from the application to be transmitted by the master to one or more slave devices must first be received in the master. This application-to-master data transfer is done in accordance with Synclk. However, the data is transmitted from the master to the one or more slave devices in accordance with tclk. The transition of such data from the rclk domain to the tclk domain is accomplished by “holding” the data in the master for some defined period of time.
Following conventional theory, CFM and CTM are identical except for their propagation direction. Thus, rclk and tclk would be similarly related, but for the finite timing delays necessarily introduced by operation of the receiver and the output driver circuits.
Unfortunately, as described in greater detail below, the ideal relationship between rclk and tclk do not hold in practice. Rather, timing delays introduced by circuit operations in varying voltage and temperature condition tend to skew the phase relationship between rclk and tclk. Recognizing that the electrical circuits in issue here will vary in their response time across a range of process, operating, and environment conditions, bus system designers must necessarily expand the synchronizing “hold” time periods within the master for data to accurately transition between the rclk and the tclk domains.
The timing diagram of FIG. 6 illustrates a set of ideal phase relationships between the clock signals described above. Consistent with contemporary practice, CTM and CFM are shown as a single signal. The phase relationship of rclk is TSETUP—IR behind CTM/CFM. Edge transitions for Synclk are synchronous with rclk. The phase relation of tclk is (90°+TOD) ahead of CTM/CFM. Thus, if the delay of a clock signal through the output driver is (90°−TSETUP—IR), then rclk and tclk will be separated in phase by 180°. These relationships are considered ideal in the working example.
Ideal sampling points for data transmitted from the application to the master correspond to the rising edge of rclk, as indicated by letters a, b, c, and d in FIG. 6. In other words, the setup and hold requirements which the application must adhere to are referenced to these edges.
However, as practically implemented within contemporary bus systems, the actual sampling of this data occurs at the falling edges of tclk, as indicated by aa, bb, cc, and dd of FIG. 6. Where the ideal phase relationships of FIG. 6 exist, the setup and hold requirements within the master consist of merely the setup and hold time of a flip-flop circuit sampling the data shifted by the input receiver setup time. Unfortunately, the ideal phase relationships of FIG. 6 rarely exist within bus systems.
To summarize, the setup time requirement for the data can be described as:TSETUP—Tdata=(TOD+TSETUP—IR−90°)+TSETUP—FF, andthe hold time requirement for the data can be described as:THOLD—Tdata=THOLD—FF−(90°−TOD−TSETUP—IR),where TSETUP—FF/THOLD—FF are the setup and hold times for the flip-flops sampling the data signals. Further, TSETUP—Tdata/THOLD—Tdata are ideally referenced from the rising edge of rclk, and the optimal value for TOD is (90°−TSETUP—IR).
In actual implementation, however, the output driver delay (TOD) is seldom equal to (90°−TSETUP—IR). In fact, the delay at the output drivers will vary with operating conditions such as voltage and temperature. As a result, the ideal phase relations shown in FIG. 6 do not exist in practice. Recognizing this result, bus system designers have been forced to adopt rather loose standards for the sampling of data at the points indicated in FIG. 6. In other words, overall system timing requirements are squeezed by the necessity to accommodate a wide range of output driver delay times. In contemporary bus systems, the resulting timing restrictions are in the order of 3 ns for setup time and 2 ns for hold time. Such restrictions are a great burden on bus systems having rclk/tclk frequencies above several hundred MHz. This is particularly true since output driver delay times tends to decrease slower than the CTM cycle times.